1. Field of the Invention
The present invention relates generally to phase-locked loop circuits and more particularly to a phase-locked loop circuit having a wide dynamic input range suitable for reducing clock skew.
2. Background Art
In some applications it is necessary to produce a clock having a fixed phase relationship to a reference clock. For example, in fault-tolerant microprocessor systems, two or more microprocessors operate in parallel, each performing the same operation on a clock-by-clock basis (lock-step). One of the microprocessors (the master) interfaces directly with the system, driving all receiving signals. The second microprocessor (the shadow), receives the outputs of the master and checks the outputs each cycle. In this manner, any fault in the master can be detected.
In order to achieve lock-step operation, the skew (phase difference) between the microprocessor clocks, must be minimized and tightly controlled. This tight control must be maintained in the presence of loading requirements that vary among application systems.
It is possible to generate an internal microprocessor clock which is phase locked to an external clock using a conventional phase-locked loop. However, such conventional phase-locked loops are not generally capable of controlling clock skew to one nanosecond (10.sup.-9 seconds) or below for microprocessor clock frequencies which can range from 5 MHZ to 50 MHz and above.
The present invention is capable of reducing clock skew to less than one nanosecond over a wide range of frequencies. The disclosed phase-locked loop circuit can be readily implemented in integrated circuit form so that it can be incorporated into the clock circuitry of a microprocessor chip and other large systems having high level noise. These and other advantages of the present invention will become apparent to those of ordinary skill in the art upon a reading of the following Detailed Description of the Invention together with the drawings.